Conventionally, bipolar logic families such as Emitter Coupled Logic (ECL) use small voltage swings to achieve high speed operation. The small logic swings require logic gates to switch a large amount of current in order to maintain acceptable noise margins. Consequently the high speed operation is obtained at the expense of relatively high power dissipation.
Gravrok and Warner have recently demonstrated a new gate architecture which uses a voltage regulating and a current limiting element in series with the gate input to produce bipolar gates having large logic swings and relatively low power dissipation (Proceedings of the 1987 IEEE Bipolar Circuits and Technology Meeting, pp. 50-53). The large logic swings result in good noise immunity.
Unfortunately, high speed operation of the Gravrock and Warner architecture is limited by a relatively long rise time.